週刊 TD4をFPGAで創る 第５号 「命令デコーダを創る」

週刊 TD4をFPGAで創る 第５号 「命令デコーダを創る」

第９章からです。
ついにシミュレーション編完結！！

命令デコーダがどのような経緯でIC２つに収まったかは渡波(2003)をご参照くださいな。

Amazon.co.jp - 渡波 郁 「CPUの創りかた」 毎日コミュニケーションズ (2003)

１．74HC10

まずは3入力NAND3つ入り！

module LOGIC_74HC10(A1, B1, C1, Y1, A2, B2, C2, Y2, A3, B3, C3, Y3);
 input A1, B1, C1, A2, B2, C2, A3, B3, C3;
 output Y1, Y2, Y3;
 
 assign Y1 = ~(A1 & B1 & C1);
 assign Y2 = ~(A2 & B2 & C2);
 assign Y3 = ~(A3 & B3 & C3);
endmodule

テストベンチはいらないよね？

２．74HC32

次に2入力OR4つ入り！

module LOGIC_74HC32(A1, B1, Y1, A2, B2, Y2, A3, B3, Y3, A4, B4, Y4);
 input A1, B1, A2, B2, A3, B3, A4, B4;
 output Y1, Y2, Y3, Y4;
 
 assign Y1 = A1 | B1;
 assign Y2 = A2 | B2;
 assign Y3 = A3 | B3;
 assign Y4 = A4 | B4;
endmodule

これもテストベンチはいらないよね？

３．命令デコーダ

いよいよ命令デコーダづくり！
気合入れていきましょう。

module InstructionDecoder(OPERATION_CODE, C_FLAG_BAR, LOAD_0, LOAD_1, LOAD_2, LOAD_3, SELECT_A, SELECT_B);
 input [3:0] OPERATION_CODE;
 input C_FLAG_BAR;
 output LOAD_0, LOAD_1, LOAD_2, LOAD_3, SELECT_A, SELECT_B;
 
 reg Vcc = 1;
 reg GND = 0;
 
 wire [1:0] w;
 
 assign SELECT_B = OPERATION_CODE[1];
 
 LOGIC_74HC32 logic_74hc32 (
  OPERATION_CODE[2], OPERATION_CODE[3], LOAD_0, 
  w[0], OPERATION_CODE[3], LOAD_1, 
  OPERATION_CODE[0], OPERATION_CODE[3], SELECT_A, 
  OPERATION_CODE[0], C_FLAG_BAR, w[1]
  );
 
 LOGIC_74HC10 logic_74hc10 (
  OPERATION_CODE[2], Vcc, Vcc, w[0], 
  Vcc, w[0], OPERATION_CODE[3], LOAD_2, 
  OPERATION_CODE[2], OPERATION_CODE[3], w[1], LOAD_3
  );
endmodule

はい！出来上がり！

テストベンチはこんな感じ！

module instruction_decoder_test;
 reg  [3:0] OPCODE;
 reg  C_FLAG_BAR;
 wire LOAD_0, LOAD_1, LOAD_2, LOAD_3, SELECT_A, SELECT_B;
 
 InstructionDecoder decoder(OPCODE, C_FLAG_BAR, LOAD_0, LOAD_1, LOAD_2, LOAD_3, SELECT_A, SELECT_B);
 
 initial begin
  $dumpfile("instruction_decoder_test.vcd");
  $dumpvars(0, instruction_decoder_test);
  $monitor ("%t: OPCODE = %b%b%b%b, C_FLAG_BAR = %b, (SELECT_B, A, LOAD_0, 1, 2, 3) = %b %b %b %b %b %b", 
   $time, OPCODE[3], OPCODE[2], OPCODE[1], OPCODE[0], C_FLAG_BAR, 
   SELECT_B, SELECT_A, LOAD_0, LOAD_1, LOAD_2, LOAD_3);

   OPCODE = 4'b0000; C_FLAG_BAR = 1'b0;
  #10 OPCODE = 4'b0001; C_FLAG_BAR = 1'b0;
  #10 OPCODE = 4'b0010; C_FLAG_BAR = 1'b0;
  #10 OPCODE = 4'b0011; C_FLAG_BAR = 1'b0;
  #10 OPCODE = 4'b0100; C_FLAG_BAR = 1'b0;
  #10 OPCODE = 4'b0101; C_FLAG_BAR = 1'b0;
  #10 OPCODE = 4'b0110; C_FLAG_BAR = 1'b0;
  #10 OPCODE = 4'b0111; C_FLAG_BAR = 1'b0;
  #10 OPCODE = 4'b1001; C_FLAG_BAR = 1'b0;
  #10 OPCODE = 4'b1011; C_FLAG_BAR = 1'b0;
  #10 OPCODE = 4'b1110; C_FLAG_BAR = 1'b0;
  #10 OPCODE = 4'b1110; C_FLAG_BAR = 1'b1;
  #10 OPCODE = 4'b1111; C_FLAG_BAR = 1'b0;
  #10 $finish;
 end
endmodule

出力結果をよーく本と見比べてね！

４．そして，完成へ…

長かったCPUづくりもいよいよ一段落です。
すべてのパーツを組み合わせましょう。

module Processor(RESET, CLOCK, INPUT, OUTPUT);
 input RESET, CLOCK;
 input [3:0] INPUT;
 output [3:0] OUTPUT;
 
 reg  Vcc = 1'b1;
 reg  GND = 1'b0;
 wire [5:0] NOT_IN_USE;
 
 wire [3:0] ROM_ADDRESS;
 wire [7:0] ROM_DATA;
 wire [3:0] OPERATION_CODE;
 wire [3:0] IMEEDIATE_DATA;
 
 wire LOAD_0, LOAD_1, LOAD_2, LOAD_3, SELECT_A, SELECT_B;
 
 wire [3:0] REGISTER_IN;
 wire [3:0] REGISTER_A_OUT;
 wire [3:0] REGISTER_B_OUT;
 wire [3:0] REGISTER_C_OUT;
 wire [3:0] REGISTER_D_OUT;
 wire [3:0] ALU_IN_A;
 wire [3:0] ALU_IN_B;
 wire CARRY_OUT, C_FLAG, C_FLAG_BAR;
 
 assign ROM_ADDRESS = REGISTER_D_OUT;
 assign OPERATION_CODE = ROM_DATA[7:4];
 assign IMEEDIATE_DATA = ROM_DATA[3:0];
 assign ALU_IN_B = IMEEDIATE_DATA;
 assign OUTPUT = REGISTER_C_OUT;
 
 ROM_16WORD  ROM(ROM_ADDRESS, ROM_DATA);
 
 InstructionDecoder Instruction_Decoder (OPERATION_CODE, C_FLAG_BAR, 
  LOAD_0, LOAD_1, LOAD_2, LOAD_3, SELECT_A, SELECT_B);
 
 LOGIC_74HC161 Register_A (RESET, CLOCK, 
  REGISTER_IN[0], REGISTER_IN[1], REGISTER_IN[2], REGISTER_IN[3], 
  GND, LOAD_0, GND, 
  REGISTER_A_OUT[0], REGISTER_A_OUT[1], REGISTER_A_OUT[2], REGISTER_A_OUT[3], 
  NOT_IN_USE[0]);
  
 LOGIC_74HC161 Register_B (RESET, CLOCK, 
  REGISTER_IN[0], REGISTER_IN[1], REGISTER_IN[2], REGISTER_IN[3], 
  GND, LOAD_1, GND, 
  REGISTER_B_OUT[0], REGISTER_B_OUT[1], REGISTER_B_OUT[2], REGISTER_B_OUT[3], 
  NOT_IN_USE[1]);
  
 LOGIC_74HC161 Register_C (RESET, CLOCK, 
  REGISTER_IN[0], REGISTER_IN[1], REGISTER_IN[2], REGISTER_IN[3], 
  GND, LOAD_2, GND, 
  REGISTER_C_OUT[0], REGISTER_C_OUT[1], REGISTER_C_OUT[2], REGISTER_C_OUT[3], 
  NOT_IN_USE[2]);
  
 LOGIC_74HC161 Register_D (RESET, CLOCK, 
  REGISTER_IN[0], REGISTER_IN[1], REGISTER_IN[2], REGISTER_IN[3], 
  Vcc, LOAD_3, Vcc, 
  REGISTER_D_OUT[0], REGISTER_D_OUT[1], REGISTER_D_OUT[2], REGISTER_D_OUT[3], 
  NOT_IN_USE[3]);
 
 LOGIC_74HC153 Register_Selector_0 (SELECT_A, SELECT_B, GND, GND, 
  REGISTER_A_OUT[0], REGISTER_B_OUT[0], REGISTER_C_OUT[0], GND, 
  REGISTER_A_OUT[1], REGISTER_B_OUT[1], REGISTER_C_OUT[1], GND,
  ALU_IN_A[0], ALU_IN_A[1]);
  
 LOGIC_74HC153 Register_Selector_1 (SELECT_A, SELECT_B, GND, GND, 
  REGISTER_A_OUT[2], REGISTER_B_OUT[2], REGISTER_C_OUT[2], GND, 
  REGISTER_A_OUT[3], REGISTER_B_OUT[3], REGISTER_C_OUT[3], GND, 
  ALU_IN_A[2], ALU_IN_A[3]);
 
 LOGIC_74HC283 ALU (GND, 
  ALU_IN_A[0], ALU_IN_A[1], ALU_IN_A[2], ALU_IN_A[3], 
  ALU_IN_B[0], ALU_IN_B[1], ALU_IN_B[2], ALU_IN_B[3], 
  REGISTER_IN[0], REGISTER_IN[1], REGISTER_IN[2], REGISTER_IN[3], 
  CARRY_OUT);
 
 LOGIC_74HC74 C_Flag (RESET, CARRY_OUT, CLOCK, Vcc, C_FLAG, C_FLAG_BAR, 
  GND, GND, GND, GND, NOT_IN_USE[4], NOT_IN_USE[5]);
 
endmodule

完成！！！！！！！！！

実際に動かしてみよう！
テストベンチは次の通り。

module processor_test;
 reg  RESET, CLOCK;
 reg  [3:0] INPUT;
 wire [3:0] OUTPUT;
 
 Processor processor(RESET, CLOCK, INPUT, OUTPUT);
 
 initial begin
  $dumpfile("processor_test.vcd");
  $dumpvars(0, processor_test);
  $monitor ("%t: CLOCK = %b, RESET = %b, INPUT = %b%b%b%b, OUTPUT = %b%b%b%b", 
   $time, CLOCK, RESET, 
   INPUT[3], INPUT[2], INPUT[1], INPUT[0], 
   OUTPUT[3], OUTPUT[2], OUTPUT[1], OUTPUT[0]);
  
  CLOCK = 0;
  RESET = 1;
  INPUT = 4'b0000;
  #400 $finish;
 end
 
 always #1
  CLOCK = ~CLOCK;
endmodule

LEDチカチカとラーメンタイマーそれぞれ動いたでしょうか？
これにて一段落。

次回予告

次回は実際にFPGAに実装してみたいと思います。（多分）

Amazon.co.jp - 渡波 郁 「CPUの創りかた」 毎日コミュニケーションズ (2003)

週刊 TD4をFPGAで創る 第４号 「ALUを創る」

週刊 TD4をFPGAで創る 第４号 「ALUを創る」

第８章からです。
頑張って記事を書くぞ！

１．74HC283

というわけで4bit Full-Adder。
P信号，G信号を使ってCarry-LookaheadなAdderにするって奴はテストによく出るよ！

module LOGIC_74HC283(CIN, A1, A2, A3, A4, B1, B2, B3, B4, S1, S2, S3, S4, COUT);
 input CIN, A1, A2, A3, A4, B1, B2, B3, B4;
 output S1, S2, S3, S4, COUT;
 
 wire [3:0] G;
 wire [3:0] P;
 wire [3:0] C;
 
 assign G[0] = ~(A1 & B1);
 assign G[1] = ~(A2 & B2);
 assign G[2] = ~(A3 & B3);
 assign G[3] = ~(A4 & B4);
 
 assign P[0] = ~(A1 | B1);
 assign P[1] = ~(A2 | B2);
 assign P[2] = ~(A3 | B3);
 assign P[3] = ~(A4 | B4);
 
 assign C[0] = CIN;
 assign C[1] = ~((~CIN & G[0]) | P[0]);
 assign C[2] = ~((~CIN & G[0] & G[1]) | (G[1] & P[0]) | P[1]);
 assign C[3] = ~((~CIN & G[0] & G[1] & G[2]) | (G[1] & G[2] & P[0]) | (G[2] & P[1]) | P[2]);
 assign COUT = ~((~CIN & G[0] & G[1] & G[2] & G[3]) | (G[1] & G[2] & G[3] & P[0]) | (G[2] & G[3] & P[1]) | (G[3] & P[2]) | P[3]);
 
 assign S1 = (C[0] ^ (~P[0] & G[0]));
 assign S2 = (C[1] ^ (~P[1] & G[1]));
 assign S3 = (C[2] ^ (~P[2] & G[2]));
 assign S4 = (C[3] ^ (~P[3] & G[3]));
endmodule

テストベンチはこんな感じ？

module logic_74hc283_test;
 reg  CIN;
 reg  [3:0] A;
 reg  [3:0] B;
 wire [3:0] S;
 wire COUT;
 
 LOGIC_74HC283 logic_74hc283(CIN, 
  A[0], A[1], A[2], A[3], 
  B[0], B[1], B[2], B[3], 
  S[0], S[1], S[2], S[3], 
  COUT);
 
 initial begin
  $dumpfile("logic_74hc283_test.vcd");
  $dumpvars(0, logic_74hc283_test);
  $monitor ("%t: A = %d, B = %d, CIN = %b, S = %d, COUT = %b", 
   $time, A, B, CIN, S, COUT);
   
   CIN = 0;
   A = 0; B = 0;
  #10 A = 1; B = 1;
  #10 A = 1; B = 2;
  #10 A = 2; B = 3;
  #10 A = 4; B = 2;
  #10 A = 4; B = 3;
  #10 A = 4; B = 5;
  #10 A = 8; B = 10;
  #10 A = 6; B = 7;
  #10 A = 12; B = 9;
  #10 $finish;
 end
endmodule

番外編

２．74HC181

物理的になくても，Verilogで書くことならできちゃうんです。簡単にね！

回路図はこんな感じです。

まったく，わけがわからないよ。
でも，なんとなーく，左右にわかれてますよね？よね？

色をつけるとわかりやすい！
それじゃあ元気よく実装しましょう！（半泣）

module LOGIC_74HC181(CIN, S0, S1, S2, S3, M, A0, A1, A2, A3, B0, B1, B2, B3, F0, F1, F2, F3, COUT, COMP, G, P);
 input CIN, S0, S1, S2, S3, M, A0, A1, A2, A3, B0, B1, B2, B3;
 output F0, F1, F2, F3, COUT, COMP, G, P;
 
 wire [3:0] D;
 wire [3:0] E;
 wire [3:0] F;
 
 assign D[0] = ~((~B0 & S1) | (B0 & S0) | A0);
 assign D[1] = ~((~B1 & S1) | (B1 & S0) | A1);
 assign D[2] = ~((~B2 & S1) | (B2 & S0) | A2);
 assign D[3] = ~((~B3 & S1) | (B3 & S0) | A3);
 assign E[0] = ~((B0 & S3 & A0) | (A0 & S2 & ~B0));
 assign E[1] = ~((B1 & S3 & A1) | (A1 & S2 & ~B1));
 assign E[2] = ~((B2 & S3 & A2) | (A2 & S2 & ~B2));
 assign E[3] = ~((B3 & S3 & A3) | (A3 & S2 & ~B3));
 
 assign F0 = ((D[0] ^ E[0]) ^ ~(CIN & ~M));
 assign F1 = ((D[1] ^ E[1]) ^ ~((CIN & E[0] & ~M) | (D[0] & ~M)));
 assign F2 = ((D[2] ^ E[2]) ^ ~((CIN & E[0] & E[1] & ~M) | (E[1] & D[0] & ~M) | (D[1] & ~M)));
 assign F3 = ((D[3] ^ E[3]) ^ ~((CIN & E[0] & E[1] & E[2] & ~M) | (E[1] & E[2] & D[0] & ~M) | (E[2] & D[1] & ~M) | (D[2] & ~M)));
 
 assign P = ~(E[0] & E[1] & E[2] & E[3]);
 assign G = ~(D[3] | (E[3] & D[2]) | (E[3] & E[2] & D[1]) | (E[3] & E[2] & E[1] & D[0]));
 assign COMP = F0 & F1 & F2 & F3;
 assign COUT = ~G | (E[3] & E[2] & E[1] & E[0] & CIN);
endmodule

網羅テストを実行するのはさすがに無理だと思うので，適当にテストベンチ書いてテストしてみるといいよ！
あと，このICはActive-LowとActive-Highで挙動が違うから注意してね！
詳しいことはデータシート読め！

番外編終わり

３．74HC74

フラグレジスタ用のフリップフロップ回路です。
奥さん！二個入りニコニコ大特価だよ！

module LOGIC_74HC74(CLR1, D1, CK1, PR1, Q1, Qb1, CLR2, D2, CK2, PR2, Q2, Qb2);
 input CLR1, D1, CK1, PR1, CLR2, D2, CK2, PR2;
 output Q1, Qb1, Q2, Qb2;
 reg  Q1, Q2;
 
 assign Qb1 = ~Q1;
 assign Qb2 = ~Q2;
 
 initial begin
  Q1 <= 1'b0;
  Q2 <= 1'b0;
 end
 
 always @(CLR1, CK1, PR1, CLR2, CK2, PR2) begin
  if(~CLR1) begin
   Q1 <= 1'b0;
  end else if(~PR1) begin
   Q1 <= 1'b1;
  end else if(CK1) begin
   Q1 <= D1;
  end
  
  if(~CLR2) begin
   Q2 <= 1'b0;
  end else if(~PR2) begin
   Q2 <= 1'b1;
  end else if(CK2) begin
   Q2 <= D2;
  end
 end
endmodule

テストベンチはこんな感じ？

module logic_74hc74_test;
 reg  CLR1, D1, CK1, PR1, CLR2, D2, CK2, PR2;
 wire Q1, Qb1, Q2, Qb2;
 
 LOGIC_74HC74 logic_74hc74(CLR1, D1, CK1, PR1, Q1, Qb1, CLR2, D2, CK2, PR2, Q2, Qb2);
 
 initial begin
  $dumpfile("logic_74hc74_test.vcd");
  $dumpvars(0, logic_74hc74_test);
  $monitor ("%t: CK1 = %b, (CLR1, PR1) = (%b, %b), D1 = %b, Q1 = %b | CK2 = %b, (CLR2, PR2) = (%b, %b), D2 = %b, Q2 = %b",
   $time, CK1, CLR1, PR1, D1, Q1, CK2, CLR2, PR2, D2, Q2);
  
  CK1 = 0; CK2 = 0;
  CLR1 = 1; CLR2 = 1;
  PR1 = 1; PR2 = 1;
  D1 = 0;  D2 = 0;
  
  #3 D1 = 1; D2 = 1;
  #1 D1 = 0; D2 = 0;
  #30 $finish;
 end
 
 always #3 CK1 = ~CK1;
 always #5 CK2 = ~CK2;
endmodule

４．8.2節までの回路

というわけで，8.2節までの回路（つまり，I/Oポートなし）を書いてみます。

module CHAPTER_8_2(CLOCK, RESET, SELECT_A, SELECT_B, LOAD_0, LOAD_1, LOAD_2, LOAD_3, ROM_DATA, ROM_ADDRESS);
 input CLOCK, RESET;
 input SELECT_A, SELECT_B, LOAD_0, LOAD_1, LOAD_2, LOAD_3;
 input [7:0] ROM_DATA;
 output [3:0] ROM_ADDRESS;
 
 reg Vcc = 1'b1;
 reg GND = 1'b0;
 wire [6:0] NOT_IN_USE;
 
 wire [3:0] REGISTER_IN;
 
 wire [3:0] REGISTER_A_OUT;
 wire [3:0] REGISTER_B_OUT;
 wire [3:0] REGISTER_C_OUT;
 wire [3:0] REGISTER_D_OUT;
 
 wire [3:0] ALU_IN_A;
 wire [3:0] ALU_IN_B;
 wire CARRY_OUT, C_FLAG;
 
 wire [3:0] OPERATION_CODE;
 wire [3:0] IMEEDIATE_DATA;
 
 assign ROM_ADDRESS = REGISTER_D_OUT;
 assign OPERATION_CODE = ROM_DATA[7:4];
 assign IMEEDIATE_DATA = ROM_DATA[3:0];
 assign ALU_IN_B = IMEEDIATE_DATA;
 
 LOGIC_74HC161 Register_A (RESET, CLOCK, 
  REGISTER_IN[0], REGISTER_IN[1], REGISTER_IN[2], REGISTER_IN[3], 
  GND, LOAD_0, GND, 
  REGISTER_A_OUT[0], REGISTER_A_OUT[1], REGISTER_A_OUT[2], REGISTER_A_OUT[3], 
  NOT_IN_USE[0]);
 
 LOGIC_74HC161 Register_B (RESET, CLOCK, 
  REGISTER_IN[0], REGISTER_IN[1], REGISTER_IN[2], REGISTER_IN[3], 
  GND, LOAD_1, GND, 
  REGISTER_B_OUT[0], REGISTER_B_OUT[1], REGISTER_B_OUT[2], REGISTER_B_OUT[3], 
  NOT_IN_USE[1]);
 
 LOGIC_74HC161 Register_C (RESET, CLOCK, 
  REGISTER_IN[0], REGISTER_IN[1], REGISTER_IN[2], REGISTER_IN[3], 
  GND, LOAD_2, GND, 
  REGISTER_C_OUT[0], REGISTER_C_OUT[1], REGISTER_C_OUT[2], REGISTER_C_OUT[3], 
  NOT_IN_USE[2]);
 
 LOGIC_74HC161 Register_D (RESET, CLOCK, 
  REGISTER_IN[0], REGISTER_IN[1], REGISTER_IN[2], REGISTER_IN[3], 
  Vcc, LOAD_3, Vcc, 
  REGISTER_D_OUT[0], REGISTER_D_OUT[1], REGISTER_D_OUT[2], REGISTER_D_OUT[3], 
  NOT_IN_USE[3]);
 
 LOGIC_74HC153 Register_Selector_0 (SELECT_A, SELECT_B, GND, GND, 
  REGISTER_A_OUT[0], REGISTER_B_OUT[0], REGISTER_C_OUT[0], GND, 
  REGISTER_A_OUT[1], REGISTER_B_OUT[1], REGISTER_C_OUT[1], GND,
  ALU_IN_A[0], ALU_IN_A[1]);
 
 LOGIC_74HC153 Register_Selector_1 (SELECT_A, SELECT_B, GND, GND, 
  REGISTER_A_OUT[2], REGISTER_B_OUT[2], REGISTER_C_OUT[2], GND, 
  REGISTER_A_OUT[3], REGISTER_B_OUT[3], REGISTER_C_OUT[3], GND, 
  ALU_IN_A[2], ALU_IN_A[3]);
 
 LOGIC_74HC283 ALU (GND, 
  ALU_IN_A[0], ALU_IN_A[1], ALU_IN_A[2], ALU_IN_A[3], 
  ALU_IN_B[0], ALU_IN_B[1], ALU_IN_B[2], ALU_IN_B[3], 
  REGISTER_IN[0], REGISTER_IN[1], REGISTER_IN[2], REGISTER_IN[3], 
  CARRY_OUT);
 
 LOGIC_74HC74 C_Flag (RESET, CARRY_OUT, CLOCK, Vcc, C_FLAG, NOT_IN_USE[4], 
  GND, GND, GND, GND, NOT_IN_USE[5], NOT_IN_USE[6]);
endmodule

だいぶCPUっぽくなってきましたね！

４．8.3節までの回路

どんどんいってみましょう！
8.3節までの回路（つまり，I/Oポートつき）を書いてみます。

module CHAPTER_8_3(CLOCK, RESET, SELECT_A, SELECT_B, LOAD_0, LOAD_1, LOAD_2, LOAD_3, ROM_DATA, ROM_ADDRESS);
 input CLOCK, RESET;
 input SELECT_A, SELECT_B, LOAD_0, LOAD_1, LOAD_2, LOAD_3;
 input [7:0] ROM_DATA;
 output [3:0] ROM_ADDRESS;
 
 reg Vcc = 1'b1;
 reg GND = 1'b0;
 wire [6:0] NOT_IN_USE;
 
 wire [3:0] REGISTER_IN;
 
 wire [3:0] REGISTER_A_OUT;
 wire [3:0] REGISTER_B_OUT;
 wire [3:0] REGISTER_C_OUT;
 wire [3:0] REGISTER_D_OUT;
 
 wire [3:0] ALU_IN_A;
 wire [3:0] ALU_IN_B;
 wire CARRY_OUT, C_FLAG;
 
 wire [3:0] OPERATION_CODE;
 wire [3:0] IMEEDIATE_DATA;
 
 assign ROM_ADDRESS = REGISTER_D_OUT;
 assign OPERATION_CODE = ROM_DATA[7:4];
 assign IMEEDIATE_DATA = ROM_DATA[3:0];
 assign ALU_IN_B = IMEEDIATE_DATA;
 assign OUTPUT = REGISTER_C_OUT;
 
 LOGIC_74HC161 Register_A (RESET, CLOCK, 
  REGISTER_IN[0], REGISTER_IN[1], REGISTER_IN[2], REGISTER_IN[3], 
  GND, LOAD_0, GND, 
  REGISTER_A_OUT[0], REGISTER_A_OUT[1], REGISTER_A_OUT[2], REGISTER_A_OUT[3], 
  NOT_IN_USE[0]);
  
 LOGIC_74HC161 Register_B (RESET, CLOCK, 
  REGISTER_IN[0], REGISTER_IN[1], REGISTER_IN[2], REGISTER_IN[3], 
  GND, LOAD_1, GND, 
  REGISTER_B_OUT[0], REGISTER_B_OUT[1], REGISTER_B_OUT[2], REGISTER_B_OUT[3], 
  NOT_IN_USE[1]);
  
 LOGIC_74HC161 Register_C (RESET, CLOCK, 
  REGISTER_IN[0], REGISTER_IN[1], REGISTER_IN[2], REGISTER_IN[3], 
  GND, LOAD_2, GND, 
  REGISTER_C_OUT[0], REGISTER_C_OUT[1], REGISTER_C_OUT[2], REGISTER_C_OUT[3], 
  NOT_IN_USE[2]);
  
 LOGIC_74HC161 Register_D (RESET, CLOCK, 
  REGISTER_IN[0], REGISTER_IN[1], REGISTER_IN[2], REGISTER_IN[3], 
  Vcc, LOAD_3, Vcc, 
  REGISTER_D_OUT[0], REGISTER_D_OUT[1], REGISTER_D_OUT[2], REGISTER_D_OUT[3], 
  NOT_IN_USE[3]);
 
 LOGIC_74HC153 Register_Selector_0 (SELECT_A, SELECT_B, GND, GND, 
  REGISTER_A_OUT[0], REGISTER_B_OUT[0], REGISTER_C_OUT[0], GND, 
  REGISTER_A_OUT[1], REGISTER_B_OUT[1], REGISTER_C_OUT[1], GND,
  ALU_IN_A[0], ALU_IN_A[1]);
  
 LOGIC_74HC153 Register_Selector_1 (SELECT_A, SELECT_B, GND, GND, 
  REGISTER_A_OUT[2], REGISTER_B_OUT[2], REGISTER_C_OUT[2], GND, 
  REGISTER_A_OUT[3], REGISTER_B_OUT[3], REGISTER_C_OUT[3], GND, 
  ALU_IN_A[2], ALU_IN_A[3]);
 
 LOGIC_74HC283 ALU (GND, 
  ALU_IN_A[0], ALU_IN_A[1], ALU_IN_A[2], ALU_IN_A[3], 
  ALU_IN_B[0], ALU_IN_B[1], ALU_IN_B[2], ALU_IN_B[3], 
  REGISTER_IN[0], REGISTER_IN[1], REGISTER_IN[2], REGISTER_IN[3], 
  CARRY_OUT);
 
 LOGIC_74HC74 C_Flag (RESET, CARRY_OUT, CLOCK, Vcc, C_FLAG, NOT_IN_USE[4], 
  GND, GND, GND, GND, NOT_IN_USE[5], NOT_IN_USE[6]);
endmodule

次回予告

ついにシミュレーション編最終回！
命令デコーダを完成させます！
そして，全てを結合させCPU全体の完成です！

乞うご期待！！！

Amazon.co.jp - 渡波 郁 「CPUの創りかた」 毎日コミュニケーションズ (2003)

週刊 TD4をFPGAで創る 第３号 「レジスタを創る」

週刊 TD4をFPGAで創る 第3号 「レジスタを創る」

第７章からです。
え，第６章？　ちゃんと読んでおいてね！

１．74HC153

４チャネルのデータセレクタですね。
真理表はデータシートでも参照してくださいな。

module LOGIC_74HC153(A, B, G1, G2, C10, C11, C12, C13, C20, C21, C22, C23, Y1, Y2);
 input A, B, G1, G2, C10, C11, C12, C13, C20, C21, C22, C23;
 output Y1, Y2;
 
 wire [3:0] temp [0:1];
 
 assign temp[0][0] = C10 & (~B) & (~A) & (~G1);
 assign temp[0][1] = C11 & (~B) & A & (~G1);
 assign temp[0][2] = C12 & B & (~A) & (~G1);
 assign temp[0][3] = C13 & B & A & (~G1);
 
 assign temp[1][0] = C20 & (~B) & (~A) & (~G2);
 assign temp[1][1] = C21 & (~B) & A & (~G2);
 assign temp[1][2] = C22 & B & (~A) & (~G2);
 assign temp[1][3] = C23 & B & A & (~G2);
 
 assign Y1 = temp[0][0] | temp[0][1] | temp[0][2] | temp[0][3];
 assign Y2 = temp[1][0] | temp[1][1] | temp[1][2] | temp[1][3];
endmodule

テストベンチはこんな感じ？

module logic_74hc153_test;
 reg  A, B;
 reg  [1:0] G;
 reg  [3:0] C0;
 reg  [3:0] C1;
 wire [1:0] Y;
 
 LOGIC_74HC153 logic_74hc153(A, B, G[0], G[1], 
  C0[0], C0[1], C0[2], C0[3], C1[0], C1[1], C1[2], C1[3], Y[0], Y[1]);
 
 initial begin
  $dumpfile("logic_74hc153_test.vcd");
  $dumpvars(0, logic_74hc153_test);
  $monitor ("%t: (B, A) = (%b, %b), G = (%b, %b), C0 = %b%b%b%b, C1 = %b%b%b%b, Y = (%b, %b)",
   $time, B, A, G[0], G[1], C0[0], C0[1], C0[2], C0[3], C1[0], C1[1], C1[2], C1[3], Y[0], Y[1]);
   
   G = 3;
   B = 0; A = 0;
   C0 = 4'b1100;
   C1 = 4'b0101;
  #10 B = 0; A = 0;
  #10 B = 0; A = 1;
  #10 B = 1; A = 0;
  #10 B = 1; A = 1;
  #10 $finish;
 end
endmodule

２．74HC161

４ビットカウンタです。
こいつをレジスタとして使います。

module LOGIC_74HC161(CLR, CK, A, B, C, D, ENP, LOAD, ENT, QA, QB, QC, QD, CO);
 input CLR, CK, A, B, C, D, ENP, LOAD, ENT;
 output QA, QB, QC, QD, CO;
 
 wire [3:0] DATA = {D, C, B, A};
 reg  [3:0] FLIPFLOP;
 
 assign QA = FLIPFLOP[0];
 assign QB = FLIPFLOP[1];
 assign QC = FLIPFLOP[2];
 assign QD = FLIPFLOP[3];
 assign CO = ENT & QA & QB & QC & QD;
 
 initial begin
  FLIPFLOP <= 4'b0000;
 end
 
 always @(CLR or posedge CK) begin
  if(~CLR) begin
   FLIPFLOP <= 4'b0000;
  end
  else if(CK) begin
   if(~LOAD) begin
    FLIPFLOP <= DATA;
   end else if(ENP & ENT) begin
    if(FLIPFLOP == 4'b1111) begin
     FLIPFLOP <= 4'b0000;
    end else begin
     FLIPFLOP <= FLIPFLOP + 1;
    end
   end
  end
 end
endmodule

テストベンチはこんな感じ？

module logic_74hc161_test;
 reg  CLR, CK, ENP, LOAD, ENT;
 reg  [3:0] DATA;
 wire A, B, C, D, QA, QB, QC, QD, CO;
 wire [3:0] Q;
 
 assign A = DATA[0];
 assign B = DATA[1];
 assign C = DATA[2];
 assign D = DATA[3];
 assign Q = {QD, QC, QB, QA};
 
 LOGIC_74HC161 logic_74hc161(CLR, CK, A, B, C, D, ENP, LOAD, ENT, QA, QB, QC, QD, CO);
 
 initial begin
  $dumpfile("a.vcd");
  $dumpvars(0, logic_74hc161_test);
  $monitor ("%t: CK = %b, (CLR, LOAD, ENP, ENT) = (%b %b %b %b), DATA = %d(%b%b%b%b), Q = %d(%b%b%b%b), CO = %b",
   $time, CK, CLR, LOAD, ENP, ENT, DATA, D, C, B, A, Q, QD, QC, QB, QA, CO);
  
   CK = 0;
   CLR = 1; ENP = 1; LOAD = 1; ENT = 1;
   DATA = 0;
  #60 
  #10  CLR = 0;
  #10  CLR = 1;
  #60  DATA = 0;
  #10  DATA = 7; LOAD = 0;
  #10  DATA = 0; LOAD = 1;
  #10  DATA = 0;
  #40  ENP = 0;
  #30  ENP = 1;
  #210
  #10  $finish;
 end
 
 always #10 CK = ~CK;
endmodule

３．第７章の章末の回路

第７章の章末の回路を実装してみましょう！

module CHAPTER_7(CLOCK, RESET, SELECT_A, SELECT_B, LOAD_0, LOAD_1, LOAD_2, LOAD_3);
 input CLOCK, RESET;
 input SELECT_A, SELECT_B, LOAD_0, LOAD_1, LOAD_2, LOAD_3;
 
 reg GND = 1'b0;
 
 wire [3:0] REGISTER_IN;
 
 wire [3:0] REGISTER_A_OUT;
 wire [3:0] REGISTER_B_OUT;
 wire [3:0] REGISTER_C_OUT;
 wire [3:0] REGISTER_D_OUT;
 
 wire [3:0] NOT_IN_USE;
 
 LOGIC_74HC161 Register_A (RESET, CLOCK, 
  REGISTER_IN[0], REGISTER_IN[1], REGISTER_IN[2], REGISTER_IN[3], 
  GND, LOAD_0, GND, 
  REGISTER_A_OUT[0], REGISTER_A_OUT[1], REGISTER_A_OUT[2], REGISTER_A_OUT[3], 
  NOT_IN_USE[0]);
 
 LOGIC_74HC161 Register_B (RESET, CLOCK, 
  REGISTER_IN[0], REGISTER_IN[1], REGISTER_IN[2], REGISTER_IN[3], 
  GND, LOAD_0, GND, 
  REGISTER_B_OUT[0], REGISTER_B_OUT[1], REGISTER_B_OUT[2], REGISTER_B_OUT[3], 
  NOT_IN_USE[1]);
 
 LOGIC_74HC161 Register_C (RESET, CLOCK, 
  REGISTER_IN[0], REGISTER_IN[1], REGISTER_IN[2], REGISTER_IN[3], 
  GND, LOAD_0, GND, 
  REGISTER_C_OUT[0], REGISTER_C_OUT[1], REGISTER_C_OUT[2], REGISTER_C_OUT[3], 
  NOT_IN_USE[2]);
 
 LOGIC_74HC161 Register_D (RESET, CLOCK, 
  REGISTER_IN[0], REGISTER_IN[1], REGISTER_IN[2], REGISTER_IN[3], 
  GND, LOAD_0, GND, 
  REGISTER_D_OUT[0], REGISTER_D_OUT[1], REGISTER_D_OUT[2], REGISTER_D_OUT[3], 
  NOT_IN_USE[3]);
 
 LOGIC_74HC153 Register_Selector_0 (SELECT_A, SELECT_B, GND, GND, 
  REGISTER_A_OUT[0], REGISTER_B_OUT[0], REGISTER_C_OUT[0], REGISTER_D_OUT[0], 
  REGISTER_A_OUT[1], REGISTER_B_OUT[1], REGISTER_C_OUT[1], REGISTER_D_OUT[1],
  REGISTER_IN[0], REGISTER_IN[1]);
 
 LOGIC_74HC153 Register_Selector_1 (SELECT_A, SELECT_B, GND, GND, 
  REGISTER_A_OUT[2], REGISTER_B_OUT[2], REGISTER_C_OUT[2], REGISTER_D_OUT[2], 
  REGISTER_A_OUT[3], REGISTER_B_OUT[3], REGISTER_C_OUT[3], REGISTER_D_OUT[3], 
  REGISTER_IN[2], REGISTER_IN[3]);
endmodule

こいつは，outputがないのでテストのしようがないですねぇ。。。
まぁ，REGISTER_A_OUTとかを無理やり出力に引っ張ればいいんですけど。
面倒なんで，テストしたい人はやって見るといいと思います。

次回予告

次はいよいよALUだよ！
演算回路だよ！
CPUっぽいよ！

Amazon.co.jp - 渡波 郁 「CPUの創りかた」 毎日コミュニケーションズ (2003)